The present invention generally relates to a method of fabricating a high integrated semiconductor device, and more specifically, to a method of fabricating a vertical transistor that improves integration of the semiconductor device according to a design rule.
Generally, a semiconductor comprises material that does not always conduct electricity and is not completely isolative. Although the semiconductor is similar to a nonconductor in a pure state, the addition of impurities or other manipulation can increase the electric conductivity of the semiconductor. Impurities are added to the semiconductor, which is then connected to a conductor to create a semiconductor device such as a transistor. A semiconductor device refers to an apparatus having various semiconductor functions. A semiconductor memory device is a representative example of a semiconductor device.
A type of semiconductor memory device includes a plurality of unit cells each including a capacitor and a transistor. A double capacitor has been used to temporarily store data. A transistor has been used to transmit data between a bit line and a capacitor corresponding to a control signal (word line) using the electric conductivity of the semiconductor that changes depending on environment. The transistor has three regions including a gate, a source and a drain. Charges between the source and drain move in response to a control signal input to the gate. The charges between the source and the drain move through a channel region in accordance with the properties of the semiconductor.
When a transistor is formed in a semiconductor substrate, a gate is formed in the semiconductor substrate, and impurities are doped at both sides of the gate to form a source and a drain. In this case, the space between the drain and the source below the gate is a channel region of the transistor. The transistor having a horizontal channel region occupies the semiconductor substrate with a given area. In the case of a complicated semiconductor device, it is difficult to reduce the occupied area due to a plurality of transistors included in the semiconductor device.
If the area of the semiconductor device is reduced, the total number semiconductor device that can be produced per wafer is increased to improve productivity. Several methods have been suggested to reduce the area of the semiconductor device. One method uses a three-dimensional transistor which includes a vertical transistor having a vertical channel region instead of a conventional horizontal transistor having a horizontal channel region.
FIGS. 1a to 1d are cross-sectional diagrams illustrating a method of fabricating a gate pattern of a vertical transistor in a general semiconductor device.
Referring to FIG. 1a, a semiconductor substrate 100 is etched with a gate pattern mask 110 to form a cylinder-type pattern. A wet etching process is performed to etch a bottom of the cylinder-type pattern, thereby obtaining a neck-shaped portion. A top portion of the cylinder-type pattern is used as a first source and drain regions 120, and a bottom portion 130 of the cylinder-type pattern is used as a neck-shaped channel region. Impurities are ion-implanted to form an active region 140 used as a second source and drain regions. The exposed semiconductor substrate is oxidized to form a gate oxide film 150.
As shown in FIG. 1b, after a gate electrode 160 is deposited to surround the bottom portion 130 of the cylinder-type pattern, the resulting structure is etched to expose the active region 140 and the semiconductor substrate 100 located below the active region 140, thereby obtaining a buried bit line 145. After isolating neighboring gate patterns arranged in direction of word line from each other through etching process, a pad oxide film 172 is formed on the exposed semiconductor substrate 100, exposed sidewall of the buried bit line 145, and exposed surface of the gate pattern including the gate pattern mask 110, the first source and drain regions 120, and the gate electrode 160.
As shown in FIG. 1c, a first insulating film 170 is filled between facing buried bit lines 145, and a damascene word line 180 for connecting the gate electrodes 160 is formed over the first insulating film 170 through a damascene process. As shown in FIG. 1d, after a second insulating film 190 is deposited over the damascene word line 180, a chemical mechanical polishing (CMP) process is performed to expose the top portion of the cylinder-type pattern that is used as the first source and drain regions 120.
FIGS. 2a and 2b are scanning acoustic microscope (SAM) photograph diagrams illustrating problems generated when the vertical transistor of FIGS. 1a to 1d are fabricated. Specifically, FIG. 2a is a plane diagram that shows a vertical transistor, and FIG. 2b is a cross-sectional diagram that shows a vertical transistor.
Referring to FIG. 2b, each vertical transistor is covered with a photoresist pattern for an etching process to form the buried bit line 145. However, a portion of the gate electrode 160 is exposed by the photoresist pattern due to misalignment when the gate electrode 160 of the vertical transistor is formed, so that a surface between the photoresist patterns is uneven. When the process margin is sufficient, the uneven surface does not affect the patterns of the transistor including the first source and drain regions 120 or the gate electrode 160 of each vertical transistor. However, since the process margin is not sufficient due to a reduction of the design rule, when an etching process is performed with the photoresist pattern, as shown in FIG. 2b, the shapes of the gate oxide film 150, the gate electrode 160 and the first source and drain regions 120 change. In this case, it is difficult to secure a normal operation of the vertical transistor.
Before the gate electrode 160 is formed, the semiconductor substrate 100 is etched, and the bottom portion 130 of the cylinder-type pattern is further etched to form a neck portion. As a result, the bottom portion 130 of the cylinder-type pattern is narrower than the top portion of the cylinder-type pattern, so that the pattern may collapse. As the design rule becomes smaller, the vertical transistor has a lower aspect ratio.
The integration of the semiconductor device has increased, and the design rule has been reduced. As a result, the aspect ratio of the vertical transistor fabricated based on the cylinder-type pattern obtained by etching the semiconductor substrate 100 has been reduced continuously. However, when the vertical transistor in the semiconductor device is fabricated by the above-described method, mis-alignment or limits due to an etching characteristic are generated while the buried bit line 145 is etched narrowly and deeply. Also, the pattern of the vertical transistor is over-etched, so that a portion of the gate oxide film 130, the gate electrode 160 and the first source and drain regions 120 may be damaged. Moreover, patterns may collapse after the etching process to form a neck portion in the bottom portion 130 of the cylinder-type pattern. As a result, the yield of the manufacturing process may be deteriorated, productivity may be degraded, and manufacturing costs may increase.